1. Field of the Invention
The present invention relates to an analog-to-digital converter. More particularly, the present invention relates to a pipelined analog-to-digital converter.
2. Description of the Related Art
Analog-to-digital conversion is a process of changing an analog signal into a digital format. In general, the value of a digital signal is determined by quantizing the analog signal. At present, most high frequency and versatile analog-to-digital converters (ADC) have a pipelined design. Typically, pipelined analog-to-digital converters are used in an environment demanding a high operating speed and a high resolution. In other words, pipelined analog-to-digital converters are frequently used for transmitting digital signals and video signals through transmission cables.
FIG. 1 is a block diagram showing the layout of a conventional pipelined analog-to-digital converter. As shown in FIG. 1 the pipelined analog-to-digital converter is a multi-stage device comprising a plurality of transfer circuits 100, 106, 108 and a decoder 105 coupled to each other. The analog-to-digital sub-converter (ADSC) 110 in each stage of transfer circuit (such as 100) samples, latches and quantizes the analog signal 101 from a previous stage to produce a digital bit signal 103. Thereafter, the quantized digital bit signal 103 is reconverted back to an analog signal 116 using the multiply digital-to-analog (MDAC) converter 115 according to a reference voltage (Vref). Through a subtractor 118, the converted analog signal 116 is subtracted from the previous analog signal 101 to produce a residual analog signal 117. The residual analog signal 117 is amplified through an amplifier 120 to produce an amplified analog signal 104 and then the amplified analog signal 104 is transmitted to the next stage. Each stage in the pipeline will perform the same set of operations to effect the analog-to-digital conversion. The digital bit signal 107 produced by the first stage of transfer circuit 106 represents the most significant bit (MSB) derived from the analog signal. Since the most significant bit is the leftmost bit in a binary number, its value is most critical in an analog-to-digital conversion. The digital bit signal 108 produced by the last stage (the nth stage) of transfer circuit 108 represents the least significant bit (LSB) derived from the analog signal. The least significant bit is the rightmost bit in a binary number.
At the end of processing the analog signal inside the first stage of transfer circuit 106, the residual analog signal will be directly transmitted to the second stage and the first stage is now free to process a newly input analog signal and so on for next and subsequent stages. The digital bit signal 103 of each transfer circuit 100 is transmitted to the decoder 105 in stages. As the residual analog signal is continuously passed from one transfer circuit to another in stages until the last stage of transfer circuit 108, the digital bit signal is also passed to the decoder 105 one by one. The decoder 105 collects and processes the digital bit signals 103, 107 and 109 produced by the transfer circuits 100, 106 and 108 to generate a final digital signal 150 that corresponds to the original input analog signal. Since each stage of transfer circuit resolves one single bit and passes the remaining signal to the next stage, the transfer circuit of a previous stage is prepared for resolving the next analog sample. If the pipelined analog-to-digital converter is a device for sampling N bits of analog signal, a total of (N/2)+1 timing cycles must pass since quantizing the first stage analog sample before the quantization of each analog sample is completed.
In the conventional technique, a reliable and effective pipelined operation often uses a non-overlapping timing signals. FIG. 2 shows a portion of a timing diagram of a conventional pipelined analog-to-digital converter. In fact, FIG. 2 shows a timing diagram of the transfer circuits 100 in FIG. 1 except the timing signals inside the decoder 105. As shown in FIGS. 1 and 2, A(n) represents a portion of the analog signal. The dash line arrow alongside A(n) indicates a pathway showing this portion of the analog signal passing from a previous stage of transfer circuit to the next stage of transfer circuit. Here, T indicates a timing cycle and nT indicates the nth current timing cycle. The timing cycle of each stage of transfer circuit comprises a sampling timing cycle and an amplifying timing cycle. The sampling timing cycle refers to the time spent for sampling, latching and quantizing the residual analog signal 101 from a previous stage by the ADSC 110 inside the transfer circuit 100 and generate the digital bit signal 103. The amplifying timing cycle refers to the time spent in transmitting the digital bit signal 103 to the MDAC 115, processing, latching and quantizing the digital bit signal 103 inside the MDAC 115 to produce an analog signal 116, transmitting the analog signal 101 of the previous stage of transfer circuit to the subtractor 118 and subtracting the analog signal 116 to produce the analog signal 117 and finally amplifying the analog signal 117 through the amplifier 120 to produce the analog signal 104.
In a non-overlapping timing signal system, half of the timing period is used for sampling while the other half is used for amplifying. In other words, the sampling period and the amplifying period are equal in length so that the amplifying period and the sampling period together constitute a single timing period. Therefore, the amplifying timing and the sampling timing both have a period of T/2. Using the transmission pathway of the analog signal A(n) as an example, the analog signal A(n) is output from the MDAC 115 and the amplifier 120 of the jth stage of transfer circuit 100 during the nT timing period. In the meantime, the ADSC 110 inside the (j+1)th transfer circuit stage 100 receives the amplified analog output A(n) from the amplifier 120 from the jth stage of transfer circuit 100. Hence, there is a direct jump from the jth amplifying period to the (j+1)th sampling period. During the timing period nT+T/2, the analog signal A(n) in the (j+1)th stage of transfer circuit 100 serves as the amplified output from the MDAC 115 and the amplifier 120. In the meantime, the ADSC 110 inside the (j+2)th stage of transfer circuit 100 receives the amplified analog data A(n) from the (j+1)th stage of transfer circuit. According to the aforementioned steps, the transfer circuit in the next stage is enabled.
In the conventional pipelined analog-to-digital converter, a portion of the time is spend in processing the signal inside the MDAC 115 while another portion of the time is spend in outputting the analog signal from the amplifier 120 during the amplifying period of the transfer circuit 100. However, the signal for sampling and quantizing is valid only after the analog signal 104 is output from the amplifier 120. Thus, when the conventional non-overlapping timing signal is used, the sampling period must wait in idle for the transition of the MDAC 115 in the previous stage and waste a lot of time. Furthermore, the amplifier 120 is needlessly set up in an enabled state to consume electric power.